1. Field of the Invention
The present invention relates to a method for manufacturing a mounting substrate on which a semiconductor chip is mounted.
2. Description of the Related Art
Presently, electronic devices using semiconductor devices such as semiconductor chips have been manufactured in high performance. Under such a circumstance, semiconductor-chips are required to be mounted on substrates in high density, and substrates on which semiconductor chips are mounted are required to be made compact and also required to save spaces.
Various types of methods for mounting semiconductor chips have been proposed, for instance, methods for mounting semiconductor chips in flip-chip manners have been proposed (referto, for example, JP-A-11-112152). While such a flip-chip mounting technique is utilized, mounting substrates in which semiconductor chips are embedded may be furthermore constructed.
However, in a case where mounting substrates on which semiconductor chips have been mounted are manufactured, there are some possibilities that below-mentioned manufacturing problems may occur.
FIG. 1A to FIG. 1C are diagrams for showing one example of sequential operations for manufacturing a mounting substrate on which a semiconductor chip is mounted.
First, in a step shown in FIG. 1A, a supporting substrate is prepared having conductive layers (for instance, copper foils, etc.) 12 and 13 formed on both faces of a core substrate 11. The core substrate 11 is made of, for example, a prepreg material.
Next, in a step as shown in FIG. 1B, a patterned connecting layer 14 is formed on the above-explained conductive layer 12, by electrolytic plating while using the conductive layer 12 as a power supply path. The connecting layer 14 is made of Au/Ni/Cu.
Next, in a step as shown in FIG. 1C, an insulating layer (build-up layer) 15 is formed on the conductive layer 12 in such a manner that the insulating layer 15 covers the connecting layer 14. In the below-mentioned steps, while the conductive layer 12 and the connecting layer 14 are used as a power supply path, via plugs and pattern wiring are formed on the connecting layer 14 by electrolytic plating so as to form a wiring section, and then the semiconductor chip is mounted on the wiring section, for example.
However, in the above-described configuration, under such a condition that the respective wiring sections on which a semiconductor chip is to be mounted are electrically connected to each other by the conductive layer 12, the semiconductor chip is mounted on these wiring sections. As a result, there is such a problem that connection tests (Short/Open Test, will be sometime referred to as “SOT”) for the individual wiring sections can be hardly carried out.
For example, in the above-explained case, the connection test of the wiring sections is carried out after the semiconductor chip is mounted and thereafter the supporting substrate is removed. As a consequence, a malfunction of a circuit (wiring) is detected after the semiconductor chip is mounted on the mounting substrate, and then the high cost semiconductor c-hip is mounted on the mounting substrate having malfunction. In this case, such a problem may occur that the semiconductor chip has to be disposed. Accordingly, there is a risk that the manufacturing cost is increased.